Current digital mobile communications systems require RF power amplifiers in the handset transmitter to have high efficiency; linearity not only at high output levels but also at low output levels. These stringent requirements arise from the need of the cellular system and to further increase the system transmission data rates and to expand the capacity.
In a portable handset for use in such system, a two or three stage power amplifier is normally used to power the transmitter--which is essential to determine the talk time and the size of the handset. In order to ensure that the battery lasts as long as possible in such a handset it is important to ensure that power consumption is minimised.
It is known that in a portable handset the power supply in the transmitter consumes 70%-80% of the battery power. It is evident therefore that a high efficiency power amplifier is important if the power consumption of the handset is to be reduced.
Normally a high output power is required for the power amplifier in the handset if the handset is at a position remote from the base station. However, the handsets will be often sufficiently close to a base section to allow operation of the amplifier at a medium or low output power level.
It is also important to maintain as high as possible the power and efficiency (PAE) for the amplifier at low and medium output levels. Again the higher linearity is required of the amplifier to reduce adjacent channel power (ACP) leakage over the whole power range--especially at high power levels.
There are contradictions in the way one achieves linearity, power and efficiency in a power amplifier design. If high linearity is required for a power amplifier it is usual to bias the amplifier at a high quiescent current such as class A. The efficiency therefore becomes low compared with class B or class C amplifiers. However, if a power amplifier is biased at a low quiescent current high efficiency for the amplifier can be achieved but the linearity of the device falls. It is usual in power amplifier design to make a trade off between efficiency, linearity and output power in conjunction with the biasing point, matching circuits and the like.
Various suggestions have been made (see bibliography and end of description)
To increase the PAE at low and high output power levels some have proposed a scheme with switch circuits. In this scheme the switch circuit and one or more amplifier circuits are introduced to improve amplifier efficiency. The first amplifier circuit is designed to achieve a high PAE at high output power levels whilst the second amplifier is designed for high PAE at low output power levels. Thus at different power levels different power amplifiers are used to amplify the input signal. Therefore the amplifier can obtain high PAE at low output power levels but unfortunately it cannot improve the linearity of the power amplifier at high output power levels.
Another approach to increase the efficiency was suggested earlier (see Sato). In this scheme the gate voltage of the amplifier is varied according to the output power levels. At low output power levels, bias current for the power amplifier is named to low to achieve high efficiency. At high output power levels bias current for the power amplifier is adjusted high to achieve high linearity. Unfortunately the power sensor and bias control circuits are required to realise the bias control function which again increases complexity of the power amplifier.